1. Field of the Invention
This invention relates to computer systems and more particularly to I/O addressing techniques employed during direct memory access operations of a DMA controller.
2. Description of the Relevant Art
In early personal computer system designs, the transfer of information between system memory and I/O addressable peripheral devices such as disk controllers, displays, keyboards and serial/parallel interface units was performed directly by the system microprocessor. As the number of transactions with peripheral devices increased and the capabilities of such devices expanded, the burden on the microprocessor associated with this transfer task severely limited overall system performance. Accordingly, techniques were developed to free the microprocessor from this task. Direct memory access (DMA) was one such developed technique.
Direct memory access is typically handled by a DMA controller which is assigned the task of coordinating and performing data transfers between system memory and a peripheral device (or other system resource) without the intervention of the microprocessor. Before a DMA transfer can begin, certain information herein referred to as "initialization data" must be provided to the DMA controller from the microprocessor to indicate the direction of the transfer to be executed (i.e., memory-to-peripheral device or peripheral device-to-memory) as well as the first address of system memory from which data is to be retrieved or to which data is to be written. The number of data words or bytes involved in the desired DMA transfer operation is further specified by the initialization data.
Following initialization, the peripheral device (or peripheral controller) can initiate the DMA transfer at any time by asserting a request signal to indicate that it is ready to receive or transmit data via a direct memory access operation. The DMA controller responsively obtains mastership of the local bus by asserting a bus request signal (referred to as a "HOLD" signal for some microprocessors). When the microprocessor detects assertion of the bus request signal, it completes the operation it is currently executing, disables its address, data, and control bus outputs, and asserts a bus acknowledge signal. The DMA controller then takes control of the local bus to perform the transfer.
The DMA controller may execute a DMA transfer using one of two basic approaches: a one-cycle transfer or a two-cycle transfer. FIG. 1 illustrates a memory-to-peripheral device transfer using the two-cycle approach. Specifically, FIG. 1 is a block diagram of a computer system that includes a microprocessor (CPU) 10, a DMA controller 12, a system memory 14, a peripheral controller 16, and a peripheral device 18. A data bus 20, an address bus 22, and a control bus 24 (referred to collectively as a local bus) interconnect microprocessor 10, DMA controller 12, system memory 14, and peripheral controller 16.
The DMA controller 12 begins the transfer by reading the first memory location of system memory 14 to be transferred and storing the data byte in a temporary register located in the DMA controller 12. The DMA controller 12 performs the read in the same manner as a typical microprocessor; it places the memory address on the address bus 22, asserts a MEMRD (memory read) control signal, and reads the data from the data bus 20. When the DMA controller 12 has completed the read cycle, it drives the data in the temporary register back onto the data bus 20, addresses the peripheral controller 16, and asserts the IOWR (I/O write) control signal. One word (or byte) of data is thereby read from the system memory 14 and is written to the peripheral device 18. The memory address is then incremented, and the process is repeated to transfer the next word. When the specified number of words have been transferred (or after each word in a cycle-stealing mode), the DMA controller 12 deasserts the bus request signal and the microprocessor 10 resumes operation from the point at which it was halted.
While the two-cycle transfer described above historically provided a great degree of flexibility, the transfer rate was typically relatively slow since two bus cycles were required for each transfer. One-cycle DMA transfers were accordingly introduced to increase the speed of DMA transfers.
To implement one-cycle transfers, a DMA acknowledge signal is typically used to take the place of the address select signals for the peripheral controller and allows the DMA controller to select an I/O port while simultaneously addressing memory. FIG. 2 is a block diagram of a computer system that illustrates a memory-to-peripheral device transfer using the one-cycle approach. Circuit blocks that correspond to those of FIG. 1 are numbered identically.
To transfer data from system memory 14 to peripheral device 18, the DMA controller 12 places the memory address on the address bus 22 and asserts the DMA acknowledge signal to select the peripheral device 18. It is noted that within such systems, a unique DMA acknowledge signal is provided to each peripheral controller (or I/O port) that can be used in a DMA transfer. The DMA controller 12 then asserts both the MEMRD and IOWR control signals. The system memory 14 responsively provides the data on the data bus 20, which is read directly by the peripheral device 18. In this situation, the data does not pass through the DMA controller 12. Since only one bus cycle is required, the DMA transfer may be accomplished relatively expeditiously.
A variety of specific DMA controllers and compatible peripheral devices have therefore developed that exploit the improved speed characteristics of the one cycle DMA transfer approach. A number of these compatible peripheral devices have become industry standards for use with, for example, computer systems based on the models 80386 and 80486 microprocessors.
Although the one-cycle approach to DMA transfers accommodates relatively high speeds of operation, it is also associated with many drawbacks. One such drawback is that an address disable signal is typically required to disable the internal address decoders of peripheral devices not involved in the DMA transfer. The address disable signal is necessary since certain peripheral devices may be mapped within a range of address locations (of I/O space) that directly corresponds to the same range of address locations of the system memory. The address disable signal prevents such peripheral devices from responding to the IOWR or IORD signal that is asserted during the DMA cycle. While this address disabling technique has been quite successful in accommodating one-cycle DMA transfers, the address disable signal requires a dedicated control line on the local bus and increases the pin-count of the associated integrated circuit packages, thus increasing overall system cost.
Yet another disadvantage of the one-cycle approach is that each device involved in the DMA transfer must be designed to recognize and respond to the protocols defined by the specialized DMA transfer cycle. This often increases the complexity in the design of, for example, the system memory, the bus bridges, and the peripheral devices.
A final noted drawback of the one-cycle approach is that the peripheral I/O addresses cannot be changed by system software and, similarly, the byte lane for multi-byte data buses cannot be changed by system software or hardware. This can limit versatility or limit system performance.
It would be desirable to provide a DMA controller and system that do not require an address disable signal for disabling the address decoders of I/O peripheral devices. It would further be desirable to provide a DMA controller and system that do not involve specialized DMA protocols to which subsystems such as the system memory must respond. It would additionally be desirable to provide a DMA controller and system that allow the byte lane of multi-byte data buses to be specified and changed by either system software or hardware. It would finally be desirable to provide a DMA controller and system that are compatible with conventional peripheral devices which support one-cycle DMA transfer protocols.